I2S (Inter-IC Sound)

I2S (Inter-IC Sound)

 I2S는 CD 플레이어, DSP, 디지털 TV 음향 등, 디지털 오디오 장치 및 기술을 위한 직렬 버스 설계이다.
 I2S 설계에서는 오디오 데이터를 클럭 신호와 분리하여 처리한다.
 데이터와 클럭 신호를 분리하면, 지터를 유발하는 시간과 관련된 에러들이 발생하지 않기 때문에 지터 방지 장치등이 필요없게 된다.
 I2S 버스는 시분할다중화 데이터 채널을 위한 회선 하나와, 워드 선택용 회선 하나, 그리고 클럭 회선 하나 등 모두 세 개의 직렬 버스 회선으로 구성된다.
□ Inter-IC Sound라는 디지털 오디오 장치를 위한 시리얼 버스
□ 3개의 시리얼 버스로 이루어져 있다.
    1) SD : Two time-division multiplexing 데이터 채널
    2) WS : 워드 선택, WS=0일 경우, 채널1(왼쪽), WS=1일 경우, 채널2(오른쪽)
    3) SCK : 클럭
□ 역시 필립스에서 개발되어졌다.

I2S는

CD 플레이어, DSP, 디지털 TV 음향 등, 디지털 오디오 장치 및 기술을 위한 직렬 버스 설계이다. I2S 설계에서는 오디오 데이터를 클럭 신호와 분리하여 처리한다.

 

데이터와 클럭 신호를 분리하면, 지터를 유발하는 시간과 관련된 에러들이 발생하지 않기 때문에 지터 방지 장치등이 필요없게 된다. I2S 버스는 시분할다중화 데이터 채널을 위한 회선 하나와, 워드 선택용 회선 하나, 그리고 클럭 회선 하나 등 모두 세 개의 직렬 버스 회선으로 구성된다.

 

 

1. PCM_OUT   : SD_OUT

 

2. PCM_IN      : SD_IN

 

3. PCM_SYNC : WS

 

4. PCM_CLK   :  SCK

 

 

1.0 INTRODUCTION

Many digital audio systems are being introduced into the consumer audio market, including compact disc, digital audio tape, digital sound processors, and digital TV-sound. The digital audio signals in these systems are being processed by a number of (V)LSI ICs,
such as:

• A/D and D/A converters;
• digital signal processors;
• error correction for compact disc and digital recording;
• digital filters;
• digital input/output interfaces.

Standardized communication structures are vital for both the equipment and the IC manufacturer, because they increase system flexibility. To this end, we have developed the inter-IC sound (I2S) bus – a serial link especially for digital audio.

 

2.0 BASIC SERIAL BUS REQUIREMENTS

The bus has only to handle audio data, while the other signals, such as sub-coding and control, are transferred separately. To minimize the number of pins required and to keep wiring simple, a 3-line serial bus is used consisting of a line for two time-multiplexed data
channels, a word select line and a clock line.

Since the transmitter and receiver have the same clock signal for data transmission, the transmitter as the master, has to generate the bit clock, word-select signal and data. In complex systems however, there may be several transmitters and receivers, which makes it
difficult to define the master. In such systems, there is usually a system master controlling digital audio data-flow between the various ICs.

 

Transmitters then, have to generate data under the control of an external clock, and so act as a slave. Figure 1 illustrates some simple system configurations and the basic interface timing.

 

Note that the system master can be combined with a transmitter or receiver, and it may be enabled or disabled under software control or by pin programming.

 

 

 

3.0 THE I2S BUS

As shown in Figure 1, the bus has three lines:

• continuous serial clock (SCK);
• word select (WS);
• serial data (SD);

and the device generating SCK and WS is the master.

 

 

 

3.1 Serial Data
Serial data is transmitted in two’s complement with the MSB first.
The MSB is transmitted first because the transmitter and receiver
may have different word lengths.

 

It isn’t necessary for the transmitterto know how many bits the receiver can handle, nor does thereceiver need to know how many bits are being transmitted.

When the system word length is greater than the transmitter word length, the word is truncated (least significant data bits are set to ‘0’) for data transmission.

 

If the receiver is sent more bits than its word length, the bits after the LSB are ignored. On the other hand, if the receiver is sent fewer bits than its word length, the missing bits are
set to zero internally. And so, the MSB has a fixed position, whereas the position of the LSB depends on the word length.

 

The transmitter always sends the MSB of the next word one clock period after the
WS changes.

Serial data sent by the transmitter may be synchronized with either the trailing (HIGH-to-LOW) or the leading (LOW-to-HIGH) edge of the clock signal.

 

However, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized
with the leading edge (see Figure 2 and Table 1).

 

 

3.2 Word Select
The word select line indicates the channel being transmitted:

• WS = 0; channel 1 (left);
• WS = 1; channel 2 (right).

WS may change either on a trailing or leading edge of the serial clock, but it doesn’t need to be symmetrical. In the slave, this signal

 

4.0 TIMING
In the I2S format, any device can act as the system master by providing the necessary clock signals. A slave will usually derive its internal clock signal from an external clock input. This means, taking into account the propagation delays between master clock and the
data and/or word-select signals, that the total delay is simply the sum of:

• the delay between the external (master) clock and the slave’s internal clock; and

• the delay between the internal clock and the data and/orword-select signals.

 

For data and word-select inputs, the external to internal clock delay is of no consequence because it only lengthens the effective set-up time (see Figure 2). The major part of the time margin is to accommodate the difference between the propagation delay of the transmitter, and the time required to set up the receiver.

All timing requirements are specified relative to the clock period or to the minimum allowed clock period of a device. This means that higher data rates can be used in the future.